Careers
SatixFy's Careers
RFIC Layout Engineer
Major Responsibilities:
As an RFIC Layout engineer you will:
- Own a full RFIC block from preliminary design to post out ( ex : Transmit path, Rx Path, LO generation )
- Be a part of the feasibility study for various topologies and RFIC
- Consider and propose alternative implementation topologies, taking into account aggressive performance and power consumption requirements
- Lead the layout implementation of the block and support post-extraction simulations
- Participate in top level integration and optimization of the full chip.
Qualifications, Experience and Competencies
- 5+ years of industry experience in analog and/or RFIC layout
- Experience in layout of multiple RFIC blocks from initial stage to Tape Out
- Solid understanding of the layout constraints, reliability requirements, tapeout sign off procedures for one more of the following processes:
- TSMC 40nm/28nm
- ST 28nm
- SiGe BiCMOS from IBM/GF
- Familiarity with the following tools:
- Cadence ADE
- Matlab
- Personal skills:
- Independent problem solving
- Awareness of schedule and priorities
- Team work, being businesslike and modest in attitude
- Sc or above in Electrical Engineering or equivalent experience
We are a company that promote a risk aware culture, ensure efficient and effective risk and compliance management practices by adhering to required standards and processes
Major Responsibilities:
As an RFIC Layout engineer you will:
- Own a full RFIC block from preliminary design to post out ( ex : Transmit path, Rx Path, LO generation )
- Be a part of the feasibility study for various topologies and RFIC
- Consider and propose alternative implementation topologies, taking into account aggressive performance and power consumption requirements
- Lead the layout implementation of the block and support post-extraction simulations
- Participate in top level integration and optimization of the full chip.
Qualifications, Experience and Competencies
- 5+ years of industry experience in analog and/or RFIC layout
- Experience in layout of multiple RFIC blocks from initial stage to Tape Out
- Solid understanding of the layout constraints, reliability requirements, tapeout sign off procedures for one more of the following processes:
- TSMC 40nm/28nm
- ST 28nm
- SiGe BiCMOS from IBM/GF
- Familiarity with the following tools:
- Cadence ADE
- Matlab
- Personal skills:
- Independent problem solving
- Awareness of schedule and priorities
- Team work, being businesslike and modest in attitude
- Sc or above in Electrical Engineering or equivalent experience
We are a company that promote a risk aware culture, ensure efficient and effective risk and compliance management practices by adhering to required standards and processes