The PRIME is a building block for an Active Flat Panel Array. It is designed to support up to 32 antenna elements and can be connected to other PRIME chip using a cascading SERDES port to build an antenna with the required G/T and EIRP.
The antenna direction/steering is done by applying a different time delay to each element compensating for the time difference the wave front is hitting each antenna element for a certain direction. Apart for the time attribute, each element can have control over other parameters like gain, equalizer, pre-distortion compensation to shape the antenna beam and to maximize the antenna efficiency. The processing that is done per antenna element is called “Beam Former.” The beam former is processing the signal in the digital domain (DSP) by using high speed ADC/DAC to sample the signal. An RFIC chip (i.e “BEAT”) is converting the RF signal to a lower frequency IF signal that is sampled by the ADC capturing the full BW of the antenna
. The signal processing inside the beam former is also compensating over antenna imperfections and is used to calibrate the antenna, compensate over variance in the RF frontend characteristics and used to match different fixed propagation delays in the antenna design, which can simplify the design.
The BF chip supports in a single chip 32 Tx elements and 32 Rx elements. Each Tx and Rx element is based on the below described architecture. This generic architecture is fully controlled and reconfigurable by an external CPU. Each Tx and Rx element is independently digitally controlled. Each BF chip is connected to his Prime chip neighbors to propagate the samples using cascading SERDES ports. Daisy chain connectivity to neighbors (previous and next) tiles through digital busses (SERDES), clock reference (L.O.) and Power lines.
Rx DBF block-diagram:
Tx DBF block-diagram: